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                          CPLD Release Notes
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DATE : October 25, 2023
TO : Intel(R) Server Board M50FCP 
SUBJECT : CPLD Release notes

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                          Product sign capsule
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FCP_BB_v3p0_RP475p4_Q20p1_std_10M50_cfm1_auto_prd.bin

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 				Add/Change
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				v3p0

 FW
	1. add midplane address(0x4E~0X51) whitelist
	gen_smbus_relay_config.h
	2. Ctrl PCH_PWROK to hold PLTRST to solve the warm reset cause ACM timeout issue
	gen_gpo_controls.h / t0_routines.h / t0_watchdog_handler.h
	
 RTL
	1. add midplane address(0x4E~0X51) whitelist
	gen_smbus_relay_config_pkg.sv
	2. Version changes to 0x1e(FCP v3p0), mailbox and SGPIO.
	3. CPLD RoT SVN value is 0x01 for production signed(mailbox 0x02).
	4. Ctrl PCH_PWROK to hold PLTRST to solve the warm reset cause ACM timeout issue 
	pfr_tnp_cyp_top.v / TNP_CYP_Main_wrapper.sv / TYP_CYP_Main.v / pfr_cyp_core.v / pfr_tnp_core.v / gen_gpo_controls_pkg.sv
	5. Version changes to 0x1d(FCP v2p9), mailbox and SGPIO.
	6. CPLD RoT SVN value is 0x01 for production signed(mailbox 0x02).
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				v2p8
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FW	
	1.475p4 about the FIFO revision back to 344p4 to avoid auto shutdown issue
	path: t0_watchdog_handler.h
RTL	
	1. add/remove spi whitelist. 01h/35h/B1h/B5h add to whitelist; 35h/B1h remove to forbidden list
	spi_filter.sv
	2. smbus_filtered_relay	/ smbus_filtered_relay_2.sv
	3. Version changes to 0x1c(FCP v2p8), mailbox and SGPIO.
	4. CPLD RoT SVN value is 0x01 for production signed(mailbox 0x02).